Method of forming the gate electrode of field effect transistor

ABSTRACT

A method includes depositing a contact etch stop layer (CESL) over a gate, a source/drain (S/D) region and an isolation feature. The method includes performing a first chemical mechanical planarization (CMP) to expose the gate. The method further includes performing a second CMP using a slurry different from the first CMP to expose the CESL over the S/D region, wherein, following the second CMP, an entire top surface of the CESL over the S/D region and over the isolation feature is substantially level with a top surface of the gate.

PRIORITY CLAIM

The present application is a continuation of U.S. application Ser. No. 15/798,779, filed Oct. 31, 2017, which is a continuation of U.S. application Ser. No. 14/437,962, filed Feb. 21, 2017, now U.S. Pat. No. 9,812,551, issued Nov. 7, 2017, which is a divisional of U.S. application Ser. No. 13/572,494, filed Aug. 10, 2012, now U.S. Pat. No. 9,589,803, issued Mar. 7, 2017, which are incorporated herein by reference in their entireties.

TECHNICAL FIELD

This disclosure relates to integrated circuit fabrication, and more particularly to a field effect transistor with a gate electrode.

BACKGROUND

As technology nodes shrink, in some integrated circuit (IC) designs, there has been a desire to replace the typically polysilicon gate electrode with a metal gate electrode to improve device performance with the decreased feature sizes. One process of forming a metal gate structure is termed a “gate last” process in which the final gate structure is fabricated “last” which allows for reduced number of subsequent processes, including high temperature processing, that must be performed after formation of the gate. Additionally, as the dimensions of transistors decrease, the thickness of the gate oxide must be reduced to maintain performance with the decreased gate length. In order to reduce gate leakage, high-dielectric-constant (high-k) gate dielectric layers are also used which allow greater physical thicknesses while maintaining the same effective thickness as would be provided by a thinner layer of the gate oxide having a low-dielectric-constant used in larger technology nodes.

However, there are challenges to implementing such features and processes in complementary metal-oxide-semiconductor (CMOS) fabrication. For example, in a “gate last” fabrication process, achieving a low gate resistance for a field effect transistor (FET) is difficult because voids are generated in the metal gate electrode after metal layer deposition for gap filling of a high-aspect-ratio trench, thereby increasing the likelihood of device instability and/or device failure. As the gate length and spacing between devices decrease, these problems are exacerbated.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features in the drawings may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a flowchart of a method of fabricating a field effect transistor comprising a gate electrode according to various aspects of the present disclosure; and

FIGS. 2-13 are cross-sectional views of a gate electrode of a field effect transistor at various stages of fabrication according to various aspects of the present disclosure.

FIG. 14 is a perspective view of a Fin field effect transistor according to various aspects of the present disclosure.

DESCRIPTION

It is understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Various features may be arbitrarily drawn in different scales for simplicity and clarity. In addition, the present disclosure provides examples based on a “gate last” metal gate structure, however, one skilled in the art may recognize applicability to other structures and/or use of other materials.

Referring to FIG. 1, illustrated is a flowchart illustrating a method 100 of fabricating a field effect transistor comprising a gate electrode according to various aspects of the present disclosure. The method 100 begins with step 102 in which a substrate is provided, wherein the substrate comprises a dummy gate electrode having a sidewall, a source/drain (S/D) region and a spacer on the sidewall distributed between the dummy gate electrode and the S/D region. The method 100 continues with step 104 in which a contact etch stop layer (CESL) is deposited over the dummy gate electrode, the S/D region and the spacer. The method 100 continues with step 106 in which an interlayer dielectric (ILD) layer is deposited over the CESL. The method 100 continues with step 108 in which a first chemical mechanical polishing (CMP) using a first slurry is performed to expose the CESL over the dummy gate electrode. The method 100 continues with step 110 in which a second CMP using a second slurry is performed to expose the dummy gate electrode. The method 100 continues with step 112 in which an upper portion of the CESL and spacer is removed. The method 100 continues with step 114 in which a third CMP using the first slurry is performed to expose the CESL over the S/D region. The discussion that follows illustrates embodiments of a field effect transistor (FET) that can be fabricated according to the method 100 of FIG. 1.

FIGS. 2-12 are schematic cross-sectional views of a gate electrode 224 of a field effect transistor (FET) 200 at various stages of fabrication according to various aspects of the present disclosure. In some embodiments, the FET 200 is a planar field effect transistor. In some embodiments, the FET 200 is a Fin field effect transistor. The FET 200 may be included in a microprocessor, a memory cell, and/or other integrated circuits (IC). In some embodiments, the performance of the operations mentioned in FIG. 1 does not produce a completed FET 200. A completed FET 200 may be fabricated using complementary metal-oxide-semiconductor (CMOS) technology processing. Accordingly, additional processes may be provided before, during, and/or after the method 100 of FIG. 1, and that some other processes may only be briefly described herein. Also, FIGS. 2 through 12 are simplified for a better understanding of the concepts of the present disclosure. For example, although the figures illustrate the FET 200, the IC may comprise a number of other devices comprising resistors, capacitors, inductors, fuses, etc.

Referring to FIG. 2 and step 102, a substrate 202 is provided. In at least one embodiment, the substrate 202 comprises a crystalline silicon substrate (e.g., wafer). In some alternative embodiments, the substrate 202 is made of some other suitable elemental semiconductor, such as diamond or germanium; a suitable compound semiconductor, such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. Further, the substrate 202 may include an epitaxial layer (epi-layer), may be strained for performance enhancement, and/or may include a silicon-on-insulator (SOI) structure.

The substrate 202 may further comprise active regions 204 (for simplicity only shown one active region) and isolation regions 206. The active regions 204 may include various doping configurations depending on design requirements. In some embodiments, the active region 204 is doped with p-type or n-type dopants. For example, the active regions 204 may be doped with p-type dopants, such as boron or BF₂; n-type dopants, such as phosphorus or arsenic; and/or combinations thereof. The active regions 204 may act as regions configured for an n-type metal-oxide-semiconductor FET (referred to as nMOSFET), or alternatively configured for a p-type MOSFET (referred to as pMOSFET).

The isolation regions 206 may be formed on the substrate 202 to isolate the various active regions 204. The isolation regions 206 may utilize isolation technology, such as local oxidation of silicon (LOCOS) or shallow trench isolation (STI), to define and electrically isolate the various active regions 204. In the depicted embodiment, the isolation region 206 includes a STI. The isolation regions 206 may comprise silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), a low-K dielectric material, other suitable materials, and/or combinations thereof. The isolation regions 206, and in the depicted embodiment, the STI, may be formed by any suitable process. As one example, the formation of the STI may include patterning the semiconductor substrate 202 by a conventional photolithography process, etching a trench in the substrate 202 (for example, by using a dry etching, wet etching, and/or plasma etching process), and filling the trench (for example, by using a chemical vapor deposition process) with a dielectric material. In some embodiments, the filled trench may have a multilayer structure such as a thermal oxide liner layer filled with silicon nitride or silicon oxide.

Then, a gate dielectric layer 212 is formed over the substrate 202. In some embodiments, the gate dielectric layer 212 may comprise silicon oxide, a high-k dielectric material or a combination thereof. A high-k dielectric material is defined as a dielectric material with a dielectric constant greater than that of SiO₂. The high-k dielectric layer comprises metal oxide. The metal oxide is selected from the group consisting of oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu and mixtures thereof. The gate dielectric layer 212 may be grown by a thermal oxidation process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, and may have a thickness less than 2 nanometers (nm).

The gate dielectric layer 212 may further comprise an interfacial layer 240 (FIG. 13) to minimize stress between the gate dielectric layer 212 and the substrate 202. The interfacial layer may be formed of silicon oxide or silicon oxynitride grown by a thermal oxidation process. For example, the interfacial layer can be grown by a rapid thermal oxidation (RTO) process or in an annealing process comprising oxygen.

Then, a dummy gate electrode 214 may be formed over the gate dielectric layer 212. In some embodiments, the dummy gate electrode 214 may comprise a single layer or a multilayer structure. In the depicted embodiment, the dummy gate electrode 214 may comprise poly-silicon. Further, the dummy gate electrode 214 may be doped poly-silicon with uniform or gradient doping. The dummy gate electrode 214 may have any suitable thickness. In the depicted embodiment, the dummy gate electrode 214 has a thickness in the range of about 30 nm to about 60 nm. The dummy gate electrode 214 may be formed using a low-pressure chemical vapor deposition (LPCVD) process.

Then, the dummy gate electrode 214 and gate dielectric layer 212 are patterned to produce the structure shown in FIG. 2. A layer of photoresist (not shown) is formed over the dummy gate electrode 214 by a suitable process, such as spin-on coating, and patterned to form a patterned photoresist feature over the dummy gate electrode 214 by a proper lithography patterning method. A width of the patterned photoresist feature is in the range of about 10 nm to 45 nm. The patterned photoresist feature can then be transferred using a dry etching process to the underlying layers (i.e., the dummy gate electrode 214 and the gate dielectric layer 212) to form a plurality of the dummy gate stacks 210. The dummy gate electrode 214 comprises a top surface 214 t and sidewalls 214 w. The photoresist layer may be stripped thereafter.

A conformal spacer material is then deposited around the gate stacks 210. In the present embodiment, the spacer material may include silicon nitride, silicon oxy-nitride, silicon carbide, or carbon-doped silicon nitride or other suitable material. The spacer material may comprise a single layer or multilayer structure. A blanket layer of the spacer material may be formed by CVD, ALD, physical vapor deposition (PVD), or other suitable technique. The blanket layer has a thickness ranging from about 5 nm to 15 nm. Then, an anisotropic etching is performed on the spacer material to form a pair of spacers 216 on sidewalls 214 w of the dummy gate electrode 214.

Then, using the gate stacks 210 and the pair of spacers 216 as hard masks, a biased etching process is performed to recess the substrate 202 that are unprotected or exposed to form the source/drain (S/D) cavities 205 in the active region 204 (shown in FIG. 3). In one embodiment, the etching process may be performed using a chemical selected from NF₃, CF₄, and SF₆ as an etching gas. In an alternative embodiment, the etching process may be performed using a solution comprising NH₄OH and H₂O₂.

Referring to FIG. 4 and step 102 in FIG. 1, subsequent to the formation of the S/D cavities 205 in the active region 204, the structure in FIG. 4 is produced by epi-growing a strained material 207 in the S/D cavities 205 to form S/D regions 208, wherein a lattice constant of the strained material 207 is different from a lattice constant of the substrate 202. In other words, each of the S/D regions 208 is at least partially disposed in the substrate 202 on one side of the dummy gate electrode 214. In some embodiments, the S/D region 208 extends above a substrate surface 202 s. In some embodiments, the S/D region 208 is entirely below the substrate surface 202 s (not shown).

In some embodiments, the strained material 207 comprises SiC or SiP for an nMOSFET. The strained material 207 such as SiC is selectively grown by a low-pressure CVD (LPCVD) process to form the S/D regions 208. In the depicted embodiment, the LPCVD process is performed at a temperature of about 400° C. to 800° C. and under a pressure of about 1 Torr to 15 Torr, using SiH₄, CH₄, and H₂ as reaction gases.

In some embodiments, the strained material 207 comprises SiGe or SiGeB for a pMOSFET. The strained material 207 such as silicon germanium (SiGe) is selectively grown by an LPCVD process to form the S/D regions 208. In one embodiment, the LPCVD process is performed at a temperature of about 660° C. to 700° C. and under a pressure of about 13 Torr to 50 Torr, using SiH₂Cl₂, HCl, GeH₄, B₂H₆, and H₂ as reaction gases.

In some embodiment, silicide regions (not shown) may be optionally formed on the S/D regions 208 by a self-aligned silicide (salicide) process. For example, the salicide process may comprise 2 steps. First, a metal material may be deposited via sputtering on the S/D regions 208 at a temperature between about 500° C. to about 900° C., causing a reaction between the underlying silicon and metal material to form the silicide regions. Then, the un-reacted metal material may be etched away. The silicide regions may comprise a material selected from titanium silicide, cobalt silicide, nickel silicide, platinum silicide, erbium silicide, and palladium silicide.

Referring to FIG. 5 and step 104 in FIG. 1, following the formation of the S/D regions 208 in the active region 204, the structure in FIG. 5 is produced by depositing a contact etch stop layer (CESL) 218 over the dummy gate electrode 214, the S/D region 208 and the spacer 216 and extending along the STI regions 206. The CESL 218 may comprise, but is not limited to, silicon nitride, silicon oxy-nitride, silicon carbide, or carbon-doped silicon nitride. The CESL 218 has a thickness in the range of about 15 nm to about 20 nm.

In some embodiments, the CESL 218 may be deposited using CVD, high density plasma (HDP) CVD, sub-atmospheric CVD (SACVD), molecular layer deposition (MLD), sputtering, or other suitable methods. For example, the MLD process of the depicted embodiment is carried out under a pressure less than 10 mTorr and in a temperature range from about 350° C. to 500° C. In at least one embodiment, the silicon nitride is deposited over the gate electrode 214, the S/D region 208 and the spacer 216 by reacting a silicon source compound and a nitrogen source. The silicon source compound provides silicon to the deposited silicon nitride and may be silane (SiH₄) or tetrathoxysilane (TEOS). The nitrogen source provides nitrogen to the deposited silicon nitride and may be ammonia (NH₃) or nitrogen gas (N₂). In another embodiment, the carbon-doped silicon nitride is deposited over the gate electrode 214, the S/D region 208 and the spacer 216 by reacting a carbon source compound, a silicon source compound, and a nitrogen source. The carbon source compound may be an organic compound, such as a hydrocarbon compound, e.g., ethylene (C₂H₆), and the silicon source compound and the nitrogen source may be the same as for the silicon nitride CESL.

Referring to FIG. 6 and step 106 in FIG. 1, after depositing the CESL 218, the structure in FIG. 6 is produced by depositing an interlayer dielectric (ILD) layer 222 over the CESL 218. The ILD layer 222 may comprise a dielectric material. The dielectric material may comprise silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), spin-on glass (SOG), fluorinated silica glass (FSG), carbon doped silicon oxide (e.g., SiCOH), Black Diamond® (Applied Materials of Santa Clara, Calif.), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCB (bis-benzocyclobutenes), Flare, SiLK® (Dow Chemical, Midland, Mich.), polyimide, and/or combinations thereof. The ILD layer 222 may comprise one or more dielectric materials and/or one or more dielectric layers. In some embodiments, the ILD layer 222 may be deposited over the CESL 218 to a suitable thickness by CVD, high density plasma (HDP) CVD, sub-atmospheric CVD (SACVD), spin-on, sputtering, or other suitable methods. In the depicted embodiment, the ILD layer 222 comprises a thickness of about 3000 Angstroms (Å) to 4500 Å.

In a gate last process, the dummy gate electrode 214 may be removed so that a resulting metal gate electrode 224 (shown in FIG. 12) may be formed in place of the dummy gate electrode 214. Accordingly, both the ILD layer 222 and the CESL 218 are planarized using CMP processes (steps 108, 110 in FIG. 1) until the top surface 214 t of the dummy gate electrode layer 214 is exposed or reached.

Referring to FIG. 7 and step 108 in FIG. 1, after depositing the ILD layer 222 over the CESL 218, the structure in FIG. 7 is produced by performing a first chemical mechanical polishing (CMP) 230 using a first slurry 232 to expose the CESL 218 over the dummy gate electrode 214. In the depicted embodiment, the first CMP 230 is performed at a head rotation speed of about 50 rpm to about 150 rpm and a platen rotation speed of about 50 rpm to about 150 rpm, and under a down force of about 1 psi to about 4 psi and a slurry flow rate of about 100 mL per minute to about 300 mL per minute. In some embodiments, the first slurry 232 comprises CeO₂.

Referring to FIG. 8 and step 110 in FIG. 1, subsequent to the first CMP 230 to expose the CESL 218, the structure in FIG. 8 is produced by performing a second CMP 234 using a second slurry 236 to expose the dummy gate electrode 214. In the depicted embodiment, the second CMP 236 is performed at a head rotation speed of about 50 rpm to about 150 rpm and a platen rotation speed of about 50 rpm to about 150 rpm, and under a down force of about 1 psi to about 4 psi and a slurry flow rate of about 100 mL per minute to about 300 mL per minute. In some embodiments, the second slurry 236 comprises SiO₂. Thus, the second CMP 234 may have a high selectivity to provide a substantially planar surface for the dummy gate electrode 214, spacers 216, CESL 218, and ILD layer 222.

In some embodiments, after the CMP processes, a gate replacement process is performed. The dummy gate electrode 214 may be removed from the gate stacks 210 surrounded with dielectric comprising the spacers 216, CESL 218, and ILD layer 222, which results in the formation of a high-aspect-ratio (e.g., greater than 3) trench in the dielectric by a wet etch and/or a dry etch process.

A metal layer then fills in the high-aspect-ratio trench. The metal layer may include any metal material suitable for forming a metal gate electrode or portion thereof, including barriers, work function layers, liner layers, interface layers, seed layers, adhesion layers, barrier layers, etc. The metal layer is formed by a PVD process.

A side effect of the PVD process is especially prone to formation of a metal overhang at a mouth of the high-aspect-ratio trench; thereby the metal overhang tends to block the mouth of the high-aspect-ratio trench. Even if this metal overhang does not actually pinch off and close the high-aspect-ratio trench, it will at least reduce a diameter of the mouth of the high-aspect-ratio trench and consequently impede further metal material from entering into the high-aspect-ratio trench and generate voids in the high-aspect-ratio trench, thereby increasing the likelihood of device instability and/or device failure.

Accordingly, the processing discussed below with reference to FIGS. 9-12 may remove at least a portion of the dummy gate electrode 214 to generate a low-aspect-ratio trench to make further depositions into the low-aspect-ratio trench easier than in a high-aspect-ratio trench. This can reduce void generation in a metal gate electrode in the low-aspect-ratio trench and improve device performance.

As depicted in FIG. 9 and step 112 in FIG. 1, for fabricating a low-aspect-ratio metal gate electrode (such as a metal gate electrode 224 shown in FIG. 12) of the FET 200, the structure in FIG. 9 is produced by removing an upper portion of the CESL 218 and spacers 216. Using the gate stack 210 and the ILD layer 222 as hard masks, a wet and/or a dry etch process is performed to recess the upper portion of the CESL 218 and spacers 216 that are unprotected or exposed to form cavities 228 lower than the top surface 214 t. In some embodiments, the wet etch process for silicon nitride CESL 218 and silicon nitride spacers 216 includes exposure to a solution containing hot H₃PO₄. In some embodiments, the dry etch process may be performed at a temperature of about 10° C. to about 70° C., under a source power of about 300 W to about 1000 W and a bias power of about 50 W to about 300 W, and under a pressure of about 10 mTorr to about 100 mTorr, using a reaction gas comprises CH₃F.

Referring to FIG. 10 and step 114 in FIG. 1, after removing an upper portion of the CESL 218 and spacers 216, the structure in FIG. 10 is produced by performing a third CMP 238 using the first slurry 232 to expose the CESL 218 over the S/D region 208, wherein the CESL 218 is adjacent to the spacer 216 and further comprising a portion 218 a extending over the S/D region 208, wherein the portion 218 a has a second top surface 218 t substantially coplanar with a first top surface 215 t of a remaining dummy gate electrode 215. The remaining dummy gate electrode 215 having a low-aspect-ratio (from about 0.8 to about 1.2). In the depicted embodiment, the third CMP 238 is performed at a head rotation speed of about 50 rpm to about 150 rpm and a platen rotation speed of about 50 rpm to about 150 rpm, and under a down force of about 1 psi to about 4 psi and a slurry flow rate of about 100 mL per minute to about 300 mL per minute. In some embodiments, the first slurry 232 comprises CeO₂.

FIG. 11 shows the FET 200 of FIG. 10 after the low-aspect-ratio remaining dummy gate electrode 215 is removed from the dummy gate stack 210 to form a low-aspect-ratio trench 226 in the pair of sidewall spacers 216. The remaining dummy gate electrode 215 may be removed using a wet etch and/or a dry etch process. In at least one embodiment, the wet etch process for dummy poly-silicon gate electrode 215 includes exposure to a hydroxide solution containing ammonium hydroxide, diluted HF, deionized water, and/or other suitable etchant solutions. In other embodiments, the dry etch process for the remaining dummy gate electrode layer 215 may be performed under a source power of about 650 W to about 800 W, a bias power of about 100 W to about 120 W, and a pressure of about 60 mTorr to about 200 mTorr, using 02, HBr and He as etching gases.

The low-aspect-ratio trench 226 makes it easier for metal material depositions into the low-aspect-ratio trench 226. Accordingly, the described methods of fabricating a low-aspect-ratio metal gate electrode 224 of the FET 200 (shown in FIG. 12) reduce void generation in the metal gate electrode 224 in the low-aspect-ratio trench 226 and improve device performance.

Referring to FIG. 12, subsequent to formation of the low-aspect-ratio trench 226, a metal layer fills the low-aspect-ratio trench 226. For example, the metal layer comprises a P-work-function metal or an N-work-function metal. In some embodiments, the P-work-function metal comprises TiN, WN, TaN, and Ru. In some embodiments, the N-work-function metal comprises Ti, Ag, Al, TiAl, TiAlN, TaC, TaCN, TaSiN, Mn, or Zr. Another CMP is performed on the metal layer to form the metal gate electrode 224 of the FET 200, wherein the CESL 218 is adjacent to the spacer 216 and further comprising a portion 218 a extending over the S/D region 208, wherein the portion 218 a has the second top surface 218 t substantially coplanar with a top surface 224 t of the metal gate electrode 224. In some embodiments, an aspect ratio of the metal gate electrode 224 is from about 0.8 to about 1.2. In the depicted embodiment, the metal gate electrode 224 and gate dielectric layer 212 are combined and referred to as a gate stack 220.

If the S/D region 208 extends above the substrate surface 202 s, a first thickness t₁ of the gate electrode 224 is greater than a second thickness t2 of the portion 218 a of the CESL 218 extending over the S/D region 208. In some embodiments, a ratio of the first thickness t₁ to the second thickness t2 is from about 1.1 to about 1.5. If the S/D region 208 is below the substrate surface 202 s (not shown), a first thickness t₁ of the gate electrode 224 is less than a second thickness t2 of the portion 218 a of the CESL 218 extending over the S/D region 208. In some embodiments, a ratio of the first thickness t₁ to the second thickness t2 is from about 0.5 to about 0.9.

After the steps shown in FIGS. 1-12 have been performed, in some embodiments, subsequent processes, comprising interconnect processing, are performed to complete the FET 200 fabrication.

FIG. 14 is a perspective view of Fin field effect transistor 300. FIG. 14 includes Fin field effect transistor similar to field effect transistor 200 as shown in FIG. 12. Similar elements in FIG. 14 have reference numbers increased by 100 over the corresponding elements in FIG. 12.

An aspect of this description relates to a method. The method includes depositing a contact etch stop layer (CESL) over a gate, a source/drain (S/D) region and an isolation feature. The method includes performing a first chemical mechanical planarization (CMP) to expose the gate. The method further includes performing a second CMP using a slurry different from the first CMP to expose the CESL over the S/D region, wherein, following the second CMP, an entire top surface of the CESL over the S/D region and over the isolation feature is substantially level with a top surface of the gate. In some embodiments, performing the second CMP includes performing the second CMP after performing the first CMP. In some embodiments, the method further includes performing a third CMP, prior to performing the first CMP, wherein the third CMP exposes a top surface of the CESL over the gate. In some embodiments, performing the third CMP includes using the slurry of the second CMP. In some embodiments, the method further includes depositing an interlayer dielectric (ILD) over the CESL. In some embodiments, performing the second CMP includes removing the ILD. In some embodiments, the method further includes replacing the gate with a replacement gate. In some embodiments, replacing the gate includes replacing the gate following performing the second CMP. In some embodiments, replacing the gate includes forming a metal gate electrode. In some embodiments, the method further includes forming the S/D region adjacent to the gate. In some embodiments, forming the S/D region includes forming a strained S/D region.

An aspect of this description relates to a method. The method includes depositing a contact etch stop layer (CESL) over a gate, a source/drain (S/D) region and an isolation feature. The method further includes depositing an interlayer dielectric (ILD) over the CESL. The method further includes performing a plurality of chemical mechanical planarization (CMP) processes, wherein a first CMP process of the plurality of CMP processes uses a different slurry from a second CMP process of the plurality of CMP processes, wherein following the plurality of CMP processes an entire top surface of the CESL over the S/D region and over the isolation feature is substantially level with a top surface of the gate. In some embodiments, the method further includes replacing the gate with a replacement gate. In some embodiments, replacing the gate includes forming a gate electrode. In some embodiments, forming the gate electrode includes forming the gate electrode having a thickness, and a ratio of the thickness to a height of the S/D region above a top surface of a substrate ranges from about 0.5 to about 0.9. In some embodiments, the method further includes etching the CESL between consecutive CMP processes of the plurality of CMP processes to expose sidewalls of the gate. In some embodiments, performing the plurality of CMP processes includes removing the ILD.

An aspect of this description relates to a method. The method includes depositing a contact etch stop layer (CESL) over a gate, a source/drain (S/D) region and an isolation feature. The method further includes performing a first chemical mechanical planarization (CMP) to expose the gate. The method further includes performing a second CMP using a slurry different from the first CMP to expose the CESL over the S/D region, wherein, following the second CMP, an entire top surface of the CESL over the S/D region and over the isolation feature is substantially level with a top surface of the gate. The method further includes replacing the gate with a replacement gate comprising a metal gate electrode. In some embodiments, replacing the gate includes replacing the gate subsequent to performing the second CMP. In some embodiments, the method further includes etching the CESL to expose sidewalls of the gate after performing the first CMP and prior to performing the second CMP.

While the invention has been described by way of example and in terms of the various embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements. 

What is claimed is:
 1. A method comprising: depositing a contact etch stop layer (CESL) over a gate, a source/drain (S/D) region and an isolation feature; performing a first chemical mechanical planarization (CMP) to expose the gate; and performing a second CMP using a slurry different from the first CMP to expose the CESL over the S/D region, wherein, following the second CMP, an entire top surface of the CESL over the S/D region and over the isolation feature is substantially level with a top surface of the gate.
 2. The method of claim 1, wherein performing the second CMP comprises performing the second CMP after performing the first CMP.
 3. The method of claim 1, further comprising performing a third CMP, prior to performing the first CMP, wherein the third CMP exposes a top surface of the CESL over the gate.
 4. The method of claim 3, wherein performing the third CMP comprises using the slurry of the second CMP.
 5. The method of claim 1, further comprising depositing an interlayer dielectric (ILD) over the CESL.
 6. The method of claim 5, wherein performing the second CMP comprises removing the ILD.
 7. The method of claim 1, further comprising replacing the gate with a replacement gate.
 8. The method of claim 7, wherein replacing the gate comprises replacing the gate following performing the second CMP.
 9. The method of claim 7, wherein replacing the gate comprises forming a metal gate electrode.
 10. The method of claim 1, further comprising forming the S/D region adjacent to the gate.
 11. The method of claim 10, wherein forming the S/D region comprises forming a strained S/D region.
 12. A method comprising: depositing a contact etch stop layer (CESL) over a gate, a source/drain (S/D) region and an isolation feature; depositing an interlayer dielectric (ILD) over the CESL; and performing a plurality of chemical mechanical planarization (CMP) processes, wherein a first CMP process of the plurality of CMP processes uses a different slurry from a second CMP process of the plurality of CMP processes, wherein following the plurality of CMP processes an entire top surface of the CESL over the S/D region and over the isolation feature is substantially level with a top surface of the gate.
 13. The method of claim 12, further comprising replacing the gate with a replacement gate.
 14. The method of claim 13, wherein replacing the gate comprises forming a gate electrode.
 15. The method of claim 14, wherein forming the gate electrode comprises forming the gate electrode having a thickness, and a ratio of the thickness to a height of the S/D region above a top surface of a substrate ranges from about 0.5 to about 0.9.
 16. The method of claim 12, further comprising etching the CESL between consecutive CMP processes of the plurality of CMP processes to expose sidewalls of the gate.
 17. The method of claim 12, wherein performing the plurality of CMP processes comprises removing the ILD.
 18. A method comprising: depositing a contact etch stop layer (CESL) over a gate, a source/drain (S/D) region and an isolation feature; performing a first chemical mechanical planarization (CMP) to expose the gate; performing a second CMP using a slurry different from the first CMP to expose the CESL over the S/D region, wherein, following the second CMP, an entire top surface of the CESL over the S/D region and over the isolation feature is substantially level with a top surface of the gate; and replacing the gate with a replacement gate comprising a metal gate electrode.
 19. The method of claim 18, wherein replacing the gate comprises replacing the gate subsequent to performing the second CMP.
 20. The method of claim 18, further comprising etching the CESL to expose sidewalls of the gate after performing the first CMP and prior to performing the second CMP. 